1. Field of the Invention
The invention relates to a fabricating method of self-aligned silicide (salicide), and more particularly to a method for preventing oxygen being implanted into substrates during the implantation of forming source/drain, and to obtain salicide with a low resistance.
2. Description of the Related Art
As the integration of the metal-oxide semiconductor (MOS) devices become higher and higher, the resistance of source/drain of a MOS device gradually increases. While it becomes comparable with the resistance of the MOS channel, to reduce the sheet resistance of drain/source and to ensure the integrity of the shallow junction between metal and MOS device, salicide process has been commonly used in the fabrication under 0.5 .mu.m.
One of the conventional salicide processes is shown as FIG. 1A to FIG. 1E. A substrate 10 on which there is at least a MOS region 11 including a gate 12, a lightly doped region 12a (LDD), and a device isolation 13, for example, a shallow trench isolation (STI), or a field oxide layer is provided. An insulation layer 14, such as a silicon oxide layer or a silicon nitride layer, is formed on the surface of the substrate 10. The insulation layer 14 is then etched back to form a spacer 15 at the side walls of the gate region 12. Meanwhile, a native oxide layer 15a is formed on the surface of the substrate 10. By using the spacer 15 and the gate 12 as masks, the substrate 10 is implanted with dopant to form a source/drain 16, as shown in FIG. 1B.
Referring to FIG. 1C, the substrate 10 is implanted by dopant such as As ions, so that a layer of amorphous silicon is formed on the surface of the silicon substrate 10. This is called the pre-amorphization effect. Then, the oxide layer 15a is removed. A metal layer 17, for example, a titanium layer, is formed on the substrate 10. Through a rapid thermal process, the metal layer 17 is reacted with the polysilicon on the surface of the gate 12 and the silicon in the surfaces of the source/drain 16 to form a salicide layer 18. The unreacted metal is then removed by wet etching. The resultant device is shown as FIG. 1D.
Referring to FIG. 1E, a dielectric layer 19 such as a silicon oxide or a silicon nitride layer is formed. The dielectric layer 19 is patterned to form a contact 20 and thus, the surfaces of source/drain 16 and part of the isolation are exposed.
The above mentioned salicide process causes a dopant effect, that is, as the dopant implanted into source/drain, the oxygen within the native oxide layer on the surface of source/drain is implanted into the source/drain with the implanted dopants. The subsequent salicide process is thus affected and the quality of the salicide is deteriorated. This effect is more serious in NMOS since the bigger As and P ions can carry more oxygen. On the contrary, the effect is not that obvious due to the smaller B ions in PMOS. Moreover, at the part of the source/drain close to the gate, leakage current is likely to happen to cause the device failure, especially at the shallow junction in the sub-micron devices.